Buy a CMODA7 from Digilant

Design a circuit board with Eaglecad - 3 boards for $80

Use the vivado synsthesis constraint

  set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]


module HBC (
    input iRstN,            //  Asynch reset
    input iHit,             //  Hit (trigger) signal from pulse detector
    output oHitDet          //  RS captured Hit detection
    );

    //  Step one.  Asynchronously capture the iHit signal from the comparator
    (* dont_touch = "true" *) wire wHD, wHD_B;
    nand #0.025 (wHD, wHD_B, ~iHit);
    nand #0.025 (wHD_B, wHD, (~iRstN));
    assign oHitDet = ~wHD_B;    //  Intentional, allows rHitCapt to dominate

endmodule


Notice the (* dont_touch = "true" *) directive. This allow loops of gates in the synthesized code