I believe in verilog, you can access the instance name with :



localparam string current_path = $sformatf("%m");

generate
if (current_path = "a.b.c.foo") begin ...


*****************************************


In VHDL we could create a random sequence based off a seed using the instance name

 seedProcess: PROCESS 
 
    variable jstr : line;
    variable jlen : integer;
    variable krnd_x : integer ;

  BEGIN
     krnd_x := 1;
     
     jstr := new string'(seedProcess'INSTANCE_NAME);
     jlen := jstr'LENGTH;
          
     for i in 1 to jlen loop
       krnd_x := (krnd_x * 17364 + (character'pos(jstr(i)))) mod 65521 mod 32768 + 1;
     end loop;

     -- Debug info
     -- write (jstr, String'(" ==> seed="));
     -- write (jstr, integer'image(krnd_x));
     -- writeline (output, jstr);
     
     GRND_Y <= krnd_x;
     
     wait;
     
  END PROCESS seedProcess;


---- Regular Signals for Pin-Check --------------------------------------------------------


A_is                 <= to_X01(A) after GDLY_A;
B_is                 <= to_X01(B) after GDLY_B;

A_undef                 <= is_X(A) ;
B_undef                 <= is_X(B) ;

----------------------------------------------------------------------------------------------------

-- ~~ core functionality 1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

-- Y_os <= NOT (A_is AND B_is); 

  cfuncProcess: PROCESS (A_is, B_is) BEGIN 
    Y_os <=  NOT (A_is AND B_is);
    IF (GRND_X = 0) THEN
      GRND_X <= GRND_Y;
    ELSE
      GRND_X <= (GRND_X * 17364) mod 65521;
    END IF;
    
    GDLY_A <= TDLY_A + ((GRND_X mod 5) / 4) * (1 ps);
    GDLY_B <= TDLY_B + ((GRND_X mod 5) / 4) * (1 ps);
  END PROCESS cfuncProcess;

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