* 9/17/2019

  Decide to ignor DNW in slam for now, so I created ggc_fixdnw.map

 This file maps the mdev65 DNW nch device to regular nch device

* ********************************************
* Thin Oxide (DNW NMOS)    3-terminal devices
* ********************************************
CMAP   mdev65:nchDNW       mdev65:nch
CMAP   mdev65:nchlvtDNW    mdev65:nchlvt
CMAP   mdev65:nchhvtDNW    mdev65:nchhvt
* ********************************************


then I run

  ggc_map.txe -m ggc_fixdnw.map ggc/PLL2019/*.sch  


Then in slam I rerun 

  slam> source import_PLL2019.tcl

* 9/16/2019
  I finally got icarus verilog to run on the gray_countd block
  I did my run in ~/Desktop/qccloc/slamvlog/



* ****************************

Now the slam schematic of the gry_countd seems to be in
slam fine.

Translators --> Spice_Out --> gray_countd.spi

  slam2eldo.bat gray_countd --> gray_countd.edo

  (all works, although I can see the DNW devices are missing models (arrgggg!!!)



Translators --> gray_countd.vls 

  slam2veri.pxe -t TSMC40 gray_countd.vls


* ****************************


Now that I have the PLL2019 library in slamwork/ggc I can import it
into slam with

cd
cd slamwork

ggc_getLib.pxe PLL2019 > import_PLL2019.tcl


now open slam

slam> source import_PLL2019.tcl

* *****************************


To copy an map PLL2019


cd
cd slamwork
cd ggc
cp -r ~/ggcckts/ggc/PLL2019 .
cd ..
ggc_map.txe -m ggc_cds2slam.map ggc/PLL2019/*.sch

ggc_browse.txe




* *****************************
At this point I have a bunch of schematics in slam now, and I have another
ggc directory in ~/ggckts

I copied my ggc directory out of g6r2h by tarring it up an then untarring it

I had to create a dummy path /icd/tools/hfl/ggcdir/ and untar the libraries
there because they are links

I tarred up the icd gcc directory (from the module area) and untarred it
here 
  Redhat:
    cd /icd/tools/hfl/ggcdir/
    tar cvf ~/zeptune/junk_ggc.tar ggc

  Xubox
    cd /icd/tools/hfl/ggcdir
    scp $CONTI:zeptune/junk_ggc.tar .
    tar xvf junk_ggc.tar

This basically installs ggc here

PROBLEM : 

  You really should install this in /ubox/ggcdir

  Then when you untar a ggc design directory from Redhat, immediately remove
  all the links REF_...

  You can then manually set up these links in the right place

ln -s $GGCDIR/ggc/libs/REF_GSAsicLib            REF_GSAsicLib
ln -s $GGCDIR/ggc/libs/REF_US_8ths              REF_US_8ths
ln -s $GGCDIR/ggc/libs/REF_analogLib            REF_analogLib
ln -s $GGCDIR/ggc/libs/REF_basic                REF_basic
ln -s $GGCDIR/ggc/libs/REF_tj18                 REF_tj18
ln -s $GGCDIR/ggc/libs/REF_tm18                 REF_tm18
ln -s $GGCDIR/ggc/libs/REF_tm40                 REF_tm40
ln -s $GGCDIR/ggc/libs/REF_warw_gen_lib         REF_warw_gen_lib
ln -s $GGCDIR/ggc/libs/REF_wfab                 REF_wfab



I need to map these 

for example in pmd65A/rc_uiv

  INSTANCE mpa mdev65:pch 55 61 0 {nf 1} {l 0.06u} {m 1} {w 1.01u} {imp_sub imp_pcc}
  INSTANCE mna mdev65:nch 55 37 0 {nf 1} {l 0.06u} {m 1} {w 730.0n} {imp_sub imp_pbb}

for example in pmd65A/rc_uiv 

  INSTANCE msbn mdev65:nchlvt 39 38 0 {nf 2} {l 0.06u} {m 1} {w 1.22u} {imp_sub PSS}
  INSTANCE ma1p mdev65:nchlvt 85 53 4 {nf 2} {l 0.06u} {m 1} {w 1.22u} {imp_sub PSS}

while in PLL2019/
  INSTANCE M32   REF_tm40:nch_lvt_macx 126 21 4 {wf 400n} {bulk PSS} {nf 6} {l 0.150u} {m 1} {imp_nch_lvt_macx_sub PSS}
  INSTANCE M31   REF_tm40:pch_macx 25 138 0 {wf 800n} {bulk PUU} {nf 8} {l 110.0n} {m 2} {imp_pch_macx_sub PUU}
  INSTANCE M2    REF_tm40:nch_macx 25 93 0 {wf 400n} {bulk PSS} {nf 8} {l 110.0n} {m 2} {imp_nch_macx_sub PSS}
  INSTANCE mn18  REF_tm40:nch_lvt_macx 325 21 0 {wf 400n} {bulk PSS} {nf 6} {l 0.150u} {m 1} {imp_nch_lvt_macx_sub PSS}
  INSTANCE mp18  REF_tm40:pch_lvt_macx 325 66 0 {wf 800n} {bulk PUU} {nf 6} {l 0.150u} {m 1} {imp_pch_lvt_macx_sub PUU}

  INSTANCE C0 analogLib:pcapacitor 116 76 0 {c 16f}

  INSTANCE I0 REF_warw_gen_lib:contiA 87 4 0 {cname gry_pinv8x} \
    {fname /icd/proj/hflroic_g6r2h/users/uia73657/sos_main/PLL2019/gry_pinv8x/schematic/sch.oa} \
    {lname PLL2019} {owner uia73657} {tstamp {Oct 23 13:58:22 2018}} {vname schematic}


(you can find a bunch of maps at greg@xubox:/media/greg/ZZLNX/jcp$ find . -name '*.map')
In order to convert from PLL2019 to slam


* ********************************************
* Thin Oxide (Regular VT)  3-terminal devices
* ********************************************
CMAP   REF_tm40:nch_macx      mdev65:nch
PMAP   mdev65:nch             {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_nch_macx_sub NULL}

CMAP   REF_tm40:pch_macx      mdev65:pch
PMAP   mdev65:pch             {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_pch_macx_sub NULL}
* ********************************************



* ********************************************
* Thin Oxide (Low     VT)  3-terminal devices
* ********************************************
CMAP   REF_tm40:nch_lvt_macx  mdev65:nchlvt
PMAP   mdev65:nchlvt          {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_nch_lvt_macx_sub NULL}

CMAP   REF_tm40:pch_lvt_macx  mdev65:pchlvt
PMAP   mdev65:pchlvt          {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_pch_lvt_macx_sub NULL}
* ********************************************



* ********************************************
* Thin Oxide (High    VT)  3-terminal devices
* ********************************************
CMAP   REF_tm40:nch_hvt_macx  mdev65:nchhvt
PMAP   mdev65:nchhvt          {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_nch_hvt_macx_sub NULL}

CMAP   REF_tm40:pch_hvt_macx  mdev65:pchhvt
PMAP   mdev65:pchhvt          {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_pch_hvt_macx_sub NULL}
* ********************************************


* ********************************************
* Thin Oxide (DNW NMOS)    3-terminal devices
* ********************************************
CMAP   REF_tm40:nch_dnw_macx     mdev65:nchDNW
PMAP   mdev65:nchDNW             {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_nch_dnw_macx_sub NULL}

CMAP   REF_tm40:nch_lvt_dnw_macx mdev65:nchlvtDNW
PMAP   mdev65:nchlvtDNW          {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_nch_lvt_dnw_macx_sub NULL}

CMAP   REF_tm40:nch_hvt_dnw_macx mdev65:nchhvtDNW
PMAP   mdev65:nchhvtDNW          {wf w} {l l} {nf nf} {m m} {bulk imp_sub}  {imp_nch_hvt_dnw_macx_sub NULL}

* ********************************************




* ********************************************
* Get rid of sheets and title blocks for now
* ********************************************
LMAP REF_warw_gen_lib  NULL
* ********************************************



  




  

* ***********************************************************************
Found a bunch of FastChip Stuff in ASTUFF.tar
I untarred this in my home directory
I then copied each aee.libname --> slamwork/ggc/libname

I actually made a bash script 

* ***********************************************************************
* ~/slamwork/get_aee.bat
* ***********************************************************************
#!/bin/bash

cp -r ../ASTUFF/aee.FastChipLib          FastChipLib
cp -r ../ASTUFF/aee.LA_TESTLA            LA_TESTLA
cp -r ../ASTUFF/aee.TC6508               TC6508
cp -r ../ASTUFF/aee.TC6508_adamw         TC6508_adamw
cp -r ../ASTUFF/aee.VSC7224B_GOLDEN      VSC7224B_GOLDEN
cp -r ../ASTUFF/aee.VSC7224C             VSC7224C
cp -r ../ASTUFF/aee.VSC7224C_GOLDEN      VSC7224C_GOLDEN
cp -r ../ASTUFF/aee.VSC7224C_deming      VSC7224C_deming
cp -r ../ASTUFF/aee.VSC7227A_GOLDEN      VSC7227A_GOLDEN
cp -r ../ASTUFF/aee.VSC7227B_PR          VSC7227B_PR
cp -r ../ASTUFF/aee.cml10                cml10
cp -r ../ASTUFF/aee.pmd65A               pmd65A


cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.analogLib   analogLib
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.basic       basic
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.mdev        mdev
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.mdev28      mdev28
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.mdev65      mdev65
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.supplies13  supplies13
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.tsmcN28     tsmcN28
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.tsmcN65     tsmcN65
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.z13lib      z13lib
cp -r /media/greg/ZZLNX/jcp/dotStuff/aee/aee.zdrv        zdrv
* ***********************************************************************



I can then automatically generate slam tcl to load in these libraries


ggc_getLib.pxe FastChipLib LA_TESTLA TC6508 TC6508_adamw VSC7224B_GOLDEN VSC7224C \
VSC7224C_GOLDEN VSC7224C_deming VSC7227A_GOLDEN VSC7227B_PR cml10 pmd65A analogLib \
basic  mdev mdev28 mdev65 tsmcN28 tsmcN65 z13lib zdrv > junk1.tcl


ggc_getLib.pxe golden346 TC141_warwar pmd65 > junk2.tcl


I want to be able to map my 40nm cells to mdev65. I don't even need slam to
do this

For example, take !/ggcckts/ggc/PLL2019/gry_pinv.sch

GRIDSCALE  10
GRAPHSCALE 1000
INSTANCE I0 REF_warw_gen_lib:contiA 87 4 0 {cname gry_pinv} {fname /icd/proj/hflroic_g6r2h/users/uia73657/sos_main/PLL2019/gry_pinv/
INSTANCE MPB REF_tm40:pch_lvt_macx 84 91 0 {wf 540.0n} {bulk PCC} {nf 1} {l 0.150u} {m 1} {imp_pch_lvt_macx_sub PCC}
INSTANCE MNA REF_tm40:nch_lvt_dnw_macx 84 61 0 {wf 260.0n} {bulk PSS} {nf 1} {l 0.150u} {m 1} {imp_nch_lvt_dnw_macx_sub PSS}
INSTANCE C0 analogLib:pcapacitor 116 76 0 {c 2f}
WIRE {126 81} {116 81}
WIRE {88 81} {116 81}
WIRE {68 98} {88 98}
WIRE {68 54} {88 54}
WIRE {88 54} {88 58}
WIRE {88 94} {88 98}
WIRE {74 61} {84 61}
WIRE {88 81} {88 88}
WIRE {116 54} {116 70}
WIRE {116 76} {116 81}
WIRE {88 54} {116 54}
WIRE {68 61} {74 61}
WIRE {74 91} {84 91}
WIRE {74 61} {74 91}
WIRE {88 64} {88 81}
PORT OUT YN 126 81 0
PORT IN PSS 68 54 0
PORT IN A 68 61 0
PORT IN PCC 68 98 0


CMAP REF_tm40:nch_mac         mdev65:nch
PMAP mdev65:nch               {Wfg wf} {fingers nf}


# ################################################################

look in /ubox/qccdir/odc/code/odcTcl.tcl

use tcl to create all the ref libs, and set them as ref libs

use aeeLoadSym and aeeLoadSch to load all the libraries .sch and .sym files

try and netlist out to veriolog



# ##################################################
proc odcOpenLib { lname } {

  global odcLibList
  global odcCfgFile

  if { [edbIsNameLibrary $lname] } {

    puts "Opening $lname which already exists"
    set id_lib [edbOpenLibrary $lname w]

  } else {

    puts "Creating $lname"
    set id_lib [edbCreateLibrary $lname $odcCfgFile]

  }

  quickAddC odcLibList $lname $id_lib
  puts "$lname ID = $id_lib"

  return true
}
# ##################################################