I can get to everything now in HTML with
file:///home/greg/csun/onkit.html
Resistors (/media/greg/ZZLNX/c5_1_2ext/c5_1_2/models/spectre/amis500cxakxx/res/)
pprnwnl --> 107 ohms/sq
nprpwnl --> 81 ohms/sq
nwrsbnl --> 770 ohms/sq
* *******************************************************************
CXOPRX --> C5X_POWER_Lib
CXASCB --> C5X_CORE_Lib
look for cdl files :
cd csun
find c5 -name '*.cdl' -exec ls -l {} \;
--> 4265 Jan 22 2016 c5/ddk/io/regular/cdl/amis500cxaprz/Rev2.000/amis500cxaprz.cdl
685192 Jul 5 2016 c5/ddk/io/regular/cdl/amis500cxoprx/Rev3.000/amis500cxoprx.cdl (Power / IO)
1057 Dec 14 2012 c5/ddk/core/levelshift/cdl/amis500cxasvm/Rev1.0/amis500cxasvm.cdl (1-cell shift)
409152 Dec 4 2014 c5/ddk/core/stdcell/cdl/amis500cxascm/Rev2.200/amis500cxascm.cdl (StdCells small)
377114 Oct 14 2014 c5/ddk/core/stdcell/cdl/amis500cxascb/Rev2.200/amis500cxascb.cdl (StdCells large)
B --> High Speed
M --> High Density
shift seems to be able to shift either way ???
From datasheet :
SHIFT is a core cell used in a mixed voltage
application. This cell level-shifts input signals
from low voltage pads to higher voltage cores or
higher voltage pads to lower voltage cores.
Output is Q.
.SUBCKT shift_m Q A LVCC LVDD LVSS SUB
*.PININFO Q:O A:I LVCC:P LVDD:P LVSS:G SUB:G
MMNMOS2 net21 A LVSS SUB enm W=5.2 L=0.6 m=1.0
MMNMOS3 Q net21 LVSS SUB enm W=2.6 L=0.6 m=1.0
MMNMOS1 net7 net10 LVSS SUB enm W=2.6 L=0.6 m=1.0
MMNMOS0 net10 A LVSS SUB enm W=2.6 L=0.6 m=1.0
MMPMOS1 net7 net21 LVDD LVDD epm W=2.4 L=0.6 m=1.0
MMPMOS3 Q net21 LVDD LVDD epm W=2.4 L=0.6 m=1.0
MMPMOS2 net21 net7 LVDD LVDD epm W=4.8 L=0.6 m=1.0
MMPMOS0 net10 A LVCC LVCC epm W=2.4 L=0.6 m=1.0
.ENDS
* *****************************************************************
cadence work area is ~/csun
There is a cdl file and gds in there
The spectre file is in :
/home/greg/simulation/gregFirst/gregCells/maestro/results/maestro/ExplorerRun.0/1/gregFirst:gregCells:1/netlist/input.scs
The layers I have in the gregCells.gds file are
In C5X
datatype 1 = pin
datatype 2 = net
datatype 4 = label
1/0 - nwell
2/0 - diff
3/0 - (NField)
4/0 - poly
4/1 - (poly pin)
5/0 - (nplus)
6/0 - (pplus)
8/0 - cont
9/0 - m1
26/0 - (poly2)
46/0 - (TERM)
55/0 - (RES)
56/0 - (CAPM)
Note - The design rules do not show layer 5 (Nplus) being drawn
You only draw pplus
Cadence has both Nplus and Pplus identical on a pmos device
NField is the same as nwell except for extended drain devices
If we are not using extended drain devices, then NField can be a derived layer
cont --> (0.5 x 0.5)
poly --> w=0.6 s=0.6 overhang_diff=0.5 space_diff=0.2 min_sdwidth=0.65
pplus --> w=0.7 s=0.7 enc_diff=0.3 spc_diff=0.3 overlap_gate=0.65 (perpendicular to width)
(note nplus is a copy of pplus, but the actual n+ implant is the opposite of this mask.
another way to say this is that in C5X, nplus is the n+ blocking mask)
******************************************************
Virtuoso Design Environment Users Guide
Chapter 7 - Specifying Environment Variables
if( boundp( 'hicAntiAliasedFonts ) then
hiSetFont( "ciw" ?size 18)
else
hiSetFont( "ciw" "-*-courier-medium-r-*-*-18-" )
)
spectre models :
/media/greg/ZZLNX/c5_1_2ext/c5_1_2/models/spectre/amis500cxakxx/Default.scs
There are indeed models for all four diodes :
include "./dio/nppwd.scs" section = mode_default
include "./dio/nwpsubd.scs" section = mode_default
include "./dio/ppnwd.scs" section = mode_default
include "./dio/schd.scs" section = mode_default
./mos/enmxr_model.scs
--------------------------
see Desktop/qccloc/JackStuff/....
also /homeLocal/c5_1_2_ext
* I had to :
LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/media/greg/ZZLNX/PVS16.13.004/tools.lnx86/K2/MaskCompose/lib/amd64/.ARCH
(for CDL output I had to get libXp.so.6 - found it in PVS above)
* When I finall get a cdl out :
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// Generated for: spectre
// Generated on: Jul 31 11:54:57 2019
// Design library name: gregFirst
// Design cell name: gregCells
// Design view name: schematic
simulator lang=spectre
global 0
include "$C5_PDK_PATH/models/spectre/amis500cxakxx/bip.scs" section=typ
include "$C5_PDK_PATH/models/spectre/amis500cxakxx/cap.scs" section=typ
include "$C5_PDK_PATH/models/spectre/amis500cxakxx/dio.scs" section=typ
include "$C5_PDK_PATH/models/spectre/amis500cxakxx/mos.scs" section=typ
include "$C5_PDK_PATH/models/spectre/amis500cxakxx/res.scs" section=typ
include "$CDS_WORKAREA/userSetup_$USER/c5/device_models.scs" section=Default
include "$CDS_WORKAREA/userSetup_$USER/c5/custom_model_libraries.spectre"
// Library name: gregFirst
// Cell name: gregCells
// View name: schematic
M3 (net21 YN PSS PSS) enm w=5.0 l=0.6 m=(4)*(3) mult=(4)*(3) region=1 \
matchingLevel="LOW"
M0 (YN A PSS PBB) enm w=5.0 l=0.6 m=(1)*(1) mult=(1)*(1) region=1 \
matchingLevel="LOW"
M1 (net22 YN PCC PCC) epm w=5.0 l=0.6 m=(3)*(2) mult=(3)*(2) region=1 \
matchingLevel="LOW"
M2 (YN A PCC PHH) epm w=5.0 l=0.6 m=(1)*(1) mult=(1)*(1) region=1 \
matchingLevel="LOW"
R0 (ZN net21) po2r l=16 w=2 ns=1 m=1 matchingLevel="LOW"
R1 (net22 ZN) npor l=16 w=4 ns=1 m=1 matchingLevel="LOW"
V0 (A 0) vsource dc=0 type=pulse val0=0 val1=3.3 period=10n rise=100p \
fall=100p width=4.9n
C0 (ZN PSS) pipc area=100.0 peri=40.0 m=1 mult=(1) matchingLevel="LOW"
V5 (PBB 0) vsource dc=0 type=dc
V4 (PSS 0) vsource dc=0 type=dc
V3 (PHH 0) vsource dc=3.3 type=dc
V1 (PCC 0) vsource dc=3.3 type=dc
simulatorOptions options psfversion="1.1.0" reltol=1e-3 vabstol=1e-6 \
iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=50n errpreset=conservative write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
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* The calibre rules files are in :
/media/greg/ZZLNX/c5_1_2ext/c5_1_2/verification/calibre
* The devices are described pretty well in the design rules
.../Desktop/qccloc/JackStuff/C5X_DSN.pdf
I can now see the c5 library is the main tech lib
You can create a new lib, and then set this as the techlib
I created a schematic "gregFirst / gregCells"
Just placing devices I get :
enm
epm
enmxr
epmxr
po2r
schd
* Cadence setup
After reading the
/homeLocal/c5_1_2ext/README_oa.txt
CDS_HOME=/homeLocal/cadence/installs/IC617
export CDS_HOME
C5_PDK_PATH=/homeLocal/c5_1_2ext/c5_1_2
export C5_PDK_PATH
ON_DK_CDS=yes
export ON_DK_CDS
* cds.lib
DEFINE c5 $C5_PDK_PATH/libs/c5/c5
DEFINE analogLib $CDS_HOME/tools.lnx86/dfII/etc/cdslib/artist/analogLib
DEFINE basic $CDS_HOME/tools.lnx86/dfII/etc/cdslib/basic
DEFINE US_8ths $CDS_HOME/tools.lnx86/dfII/etc/cdslib/sheets/US_8ths
DEFINE rfLib $CDS_HOME/tools.lnx86/dfII/samples/artist/rfLib
DEFINE cdsDefTechLib $CDS_HOME/tools.lnx86/dfII/etc/cdsDefTechLib
DEFINE gregFirst /home/greg/csun/gregFirst
------------------------------------------
calibre -drc drc.rf
c53lm=1
export c53lm
scp qoffeene@qoffee.net:cactus/cac07/bin/msamod.py .
cloc.pxe drc_results.db
main.py -m auto -l . -p /homeLocal/c5_1_2ext/c5_1_2/dotFiles/userSetupProjDir/proc_opt/