When you want to capture data from a fast domain (CLK) with a divided clock (CLK8)
  CLK8 must transition on the negedge of CLK, and then capture data from the CLK  domain on posedge of CLK8

When you want to capture data from a slow domain (CLK8) with the faster clock (CLK)
  CLK8 must transition on the posedge of CLK, and then capture data from the CLK8 domain on posedge of CLK