* AXI Nice Intro : https://adaptivesupport.amd.com/s/article/1053914?language=en_US * Installing Vivado 2/16/2024 8 ********************************************************************************************** Install Vivado, Vitis https://www.xilinx.com/support/download.html Create an account Click the link : AMD Unified Installer for FPGAs & Adaptive SoCs 2023.2: Windows Self Extracting Web Installer (EXE - 203.13 MB) 8 ********************************************************************************************** 8 ********************************************************************************************** Get Zybo Z7-10 specific stuff : Master.xdc file : https://digilent.com/reference/programmable-logic/zybo-z7/start (Master XDC Files) Zybo-Z7-Master.xdc Boad Files : https://digilent.com/reference/programmable-logic/zybo-z7/start (Tutorials – Installing Vivado, Vitis, and Digilient Board Files) Scroll down to “Install Digilent’s Board Files” Click “Download the most recent “Master Branch ZIP Archive”  This downloads the file “vivado-boards-master.zip” Extract this and make directory and copy into  C:\Xilinx\Vivado\2021.2\data\boards\board_files * The classic way to have a flipflop with reset is : always @(posedge CLK or posedge RST) begin if (RST) begin Q <= 0; end else begin Q <= D; end end A big mistake however is to put something in the "else" section that is not if the RST section. For example if I have two flipflops, and the first one is resetible, and the second one isn't, I might be tempted to do : // ************************************************ // * Horrible!! - Don't do this!!! // ************************************************ always @(posedge CLK or posedge RST) begin if (RST) begin Q0 <= 0; end else begin Q0 <= D; Q1 <= Q0; end end // ************************************************ Instead do this // ************************************************ // * Good Version - Do it like this!!! // ************************************************ always @(posedge CLK or posedge RST) begin if (RST) begin Q0 <= 0; end else begin Q0 <= D; end end always @(posedge CLK) begin Q1 <= Q0; end // ************************************************ This makes sense, but think about it a little more closely. You are saying that you want Q0 to be reset if RST is high, which makes sense, and you don't care about resetting Q1, so you think it can use simpler hardware. However, think about this. When RST is high, this code prevents Q1 from getting updated, so the clock must be gated, or some other really complicated logic must be added. * In an xdc file, an object must be a direct call to get_* A good method is : 1. Find the net name of all the BUFG outputs get_nets -of_objects [get_pins -filter {DIRECTION == OUT && REF_NAME == BUFG}] >> CLKOUT0_BUFG CK7 2. Define a pin name associated with each of these (notice the pattern match {NAME = *xxx*} set CK7_PIN [get_pins -of_objects [get_nets -of_objects [get_pins -filter {DIRECTION == OUT && REF_NAME == BUFG}] -filter {NAME =~ *CK7*}] -filter {DIRECTION == OUT}] set CLK300_PIN [get_pins -of_objects [get_nets -of_objects [get_pins -filter {DIRECTION == OUT && REF_NAME == BUFG}] -filter {NAME =~ *CLKOUT*}] -filter {DIRECTION == OUT}] ( CK7_PIN is the actual name of the pin, but you still have to call [get_pins $CK7_PIN] in an xdc file to use it ) 3. Now use [get_pins $CK7_PIN] in xdc file create_generated_clock -name CLK300 [get_pins $CLK300_PIN] create_generated_clock -name CLKRTL -source [get_pins $CLK300_PIN] -edges {1 7 15} [get_pins $CK7_PIN] * ************************************************************************************************************************************************************************************** * ************************************************************************************************************************************************************************************** * ************************************************************************************************************************************************************************************** * Print the pin properties foreach obj [get_pins -of_objects [get_cells -filter { REF_NAME == BUFG }] -filter {DIRECTION == OUT}] { puts "* *******************************" report_property $obj puts "" } * Print the net properties foreach obj [get_nets -of_objects [get_pins -of_objects [get_cells -filter { REF_NAME == BUFG }] -filter {DIRECTION == OUT}]] { puts "* *******************************" report_property $obj puts "" } It seems very useful when creating a clock in a schematic to place a BUFG directly in the RTL This makes it easy to find the net in the .xdc file in order to make a timing constraint // * ***************************************************************** // * XDC : Begin ***************************************************** // * ***************************************************************** set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { CLK125 }]; #IO_L12P_T1_MRCC_35 Sch=sysclk create_clock -name CKM -period 8.0 [get_ports { CLK125 }] create_generated_clock -name CLK300 [get_pins PLLE2_BASE_inst/CLKOUT0] create_generated_clock -name CLKRTL -source [get_pins PLLE2_BASE_inst/CLKOUT0] -edges {1 7 15} [get_nets CK7] // * ***************************************************************** // * XDC : End ***************************************************** // * ***************************************************************** // * ***************************************************************** // * RTL : Begin ***************************************************** // * ***************************************************************** reg [2:0] QFST; wire CK7; BUFG xclkr7 (.O(CK7), .I(QFST[2])); always @(posedge CLKOUT0 or posedge RST) begin if (RST == 1) begin QFST <= 0; end else begin QFST <= (QFST == 3'd6) ? 0 : (QFST + 1); end end // * ***************************************************************** // * RTL : End ***************************************************** // * ***************************************************************** * ************************************************************************** * Use DONT_TOUCH in verilog file to preserve gates PDF : ug912-vivado-properties-en-us-2023.2.pdf (see p.186 - DONT_TOUCH) module ring5( output Z0, output Z1, output Z2, output Z3, output Z4 ); (* DONT_TOUCH = "TRUE" *) LUT1 #(.INIT(2'b01)) xinv0 (.O(Z0), .I0(Z4)); (* DONT_TOUCH = "TRUE" *) LUT1 #(.INIT(2'b01)) xinv1 (.O(Z1), .I0(Z0)); (* DONT_TOUCH = "TRUE" *) LUT1 #(.INIT(2'b01)) xinv2 (.O(Z2), .I0(Z1)); (* DONT_TOUCH = "TRUE" *) LUT1 #(.INIT(2'b01)) xinv3 (.O(Z3), .I0(Z2)); (* DONT_TOUCH = "TRUE" *) LUT1 #(.INIT(2'b01)) xinv4 (.O(Z4), .I0(Z3)); endmodule * Examples report_property -all [get_ports {CK} ] set CK_PORT [get_ports {CK}] get_property PACKAGE_PIN $CK_PORT * Timing Constraints https://www.xilinx.com/video/hardware/creating-basic-clock-constraints.html https://www.xilinx.com/video/hardware/advanced-clock-constraints-and-analysis.html report_clocks report_clock_interaction report_clock_networks set_clock_group create_generated_clock -edges -edge_shift set_input_delay Virtual Clocks - clocks not associated with any actual port In TCL window : create_clock -h create_generated_clock -h set_clock_group -h set_input_delay -h set_property -h * HDMI (see email jan 19, 2021) HDMI TX ------- CKP H16 CKN H17 D0P D19 D0N D20 D1P C20 D1N B20 D2P B19 D2N A20 * wave info -h open_wave_config -h * close_wave_config * create_wave_config * open_wave_database * save_wave_config C:/Users/warwargr/AppData/Roaming/Xilinx/Vivado https://docs.xilinx.com/r/en-US/ug900-vivado-logic-simulation/Y-Axis-Zoom-Gestures-for-Analog-Waveforms https://docs.xilinx.com/r/en-US/ug908-vivado-programming-debugging/Bus-Bit-Order (see section on zoom gestures) sadly there is no good way to zoom the xaxis with TCL in Vivado foreach cmdstr [info commands] { puts $cmdstr } * Xilinx User Manuals https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0010-vivado-simulation-hub.html https://www.xilinx.com/support/documentation-navigation/design-hubs.html $BB/Manual/Xilinx * Zync Zybo-Z7 - You can get the PDF reference manual, technical ref manual, schematic, xdc files all from https://digilent.com/reference/programmable-logic/zybo-z7/start (you can get here by going to digilent.com --> click "Reference" Tab at the top rather than "Shop", then find Zybo-Z7 board) - I downloaded vivado-board-master.zip (see below) I unzipped it, and then navigated to new/board_files I then created the directory C:\Xilinx\Vivado\2021.2\data\boards\board_files I then copied all of the board files into here from the zip file (see below for how I found this master.zip file) 8888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888 - main starting point for Zybo-Z7 https://digilent.com/shop/zybo-z7-zynq-7000-arm-fpga-soc-development-board/ According to this manual, since we have a Rev D board, the QSPI memory should be Winbond --> W25Q128JV According to this manual in section 5, the board files are available from : https://digilent.com/reference/programmable-logic/zybo-z7/start This in turn takes you to : https://github.com/Digilent/vivado-boards This has the file and also leads you to https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files Which again takes you to : https://github.com/Digilent/vivado-boards It seems you need to simply get the master.zip - online manual (This one may require Vitis) https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi (This one looks like HDL only) https://digilent.com/reference/programmable-logic/zybo-z7/demos/xadcI (This may be the best getting started place) https://digilent.com/reference/programmable-logic/guides/getting-started-with-vivado * BASYS 3 Board Web Ref : https://digilent.com/reference/learn/programmable-logic/tutorials/basys-3-programming-guide/start I have a working program /Users/gooyw/project_gray9/project_gray9.xprj For this project I have saved the Sources and Contraints (and actually point to these) $DD/esp32/fpga/Sources/grayBlock9.v $DD/esp32/fpga/Sources/grayBlock9.xdc The board "Project part" is : xc7a35ticpg236-1L It is very important that you put proper delay statements in the .xdc file set_output_delay -clock CLK 0.0 [get_ports {GREG[31]}] set_output_delay -clock CLK 0.0 [get_ports {GREG[30]}] set_output_delay -clock CLK 0.0 [get_ports {GREG[29]}] set_output_delay -clock CLK 0.0 [get_ports {GREG[28]}] set_output_delay -clock CLK 0.0 [get_ports {GREG[27]}] set_output_delay -clock CLK 0.0 [get_ports {GREG[26]}] set_output_delay -clock CLK 0.0 [get_ports {GREG[25]}] set_output_delay -clock CLK 0.0 [get_ports {GREG[24]}] This is essential for the systhesis and implementation to get the clock tree correct! There are three ways to load the code (need to follow up on this) QSPI JTAG USB The simplest is USB Bitstream File : C:/Users/gooyw/project_gray9/project_gray9.runs/impl_1/grayBlock.bit Right Click "Generate Bitstream", and turn on option "-bin_file" Add Configuration Memory "mx25l3233f-spi-x1_x2_x4" It will ask to do it now, and chose the ".bin" file generated