The gain of a negative feedback loop needs to fall with frequency below unity before too much phase shift occurs unless your aim actually is to make an oscillator[1]. This idea can be applied to the stability analysis of a Switch Mode Power Supply(SMPS). Even though a SMPS is an intrinsically non-linear circuit with no small-signal linear equivalent circuit, there typically is an analog feedback loop operating on the filtered, switched output.
There are two issues involved in determining the loop gain of a SMPS (i) obtaining the open loop gain from the closed loop system and (ii) ignoring the switching waveform by averaging over a switching cycle and/or using Fourier analysis to ignore the switching frequency components. The first issue is common to most stability analysis of feedback loops. Stability analysis is based on the open loop response but if you break the feedback loop to measure open loop response directly, the circuit doesn't work anymore which was why feedback was used in the first place. The second issue arises from the fact that a SMPS is an intrinsically non-linear circuit and linear feedback theory is basically restricted to the hypothetical waveform averaged over a switching cycle.
Determining the open loop response of a linear, closed loop system is a problem solved well by Middlebrook's method[2]. That method uses test signals injected into the closed loop system to independently solve for the voltage and current gains. These two gains are then convoluted together to get the true loop gain. If a point in the feedback loop can be identified where a low impedance drives a high impedance, then the current gain is zero and it is sufficient to measure only the voltage gain and identify that as the loop gain. Such a point can normally be found in a SMPS since you have a power supply output driving an error amplifier input.
Laboratory measurement of a SMPS loop gain is automated with
commercial instrumentation pioneered by Venable Corporation and now
also available from other companies. The technique of using injected
test signals and Fourier analysis is called Frequency Response
Analysis(FRA). While this method is routine in the lab, not everyone
is aware of how to use it simulation. This article explains how to
do FRA in LTspice XVII. The method uses the voltage gain part of the
Middlebrook method, .measure statements to do the Fourier transform,
a step statement to sweep frequency, and the feature in LTspice that
allows one to plot the results of .measure statements. In reading
through the steps below, you might want to refer to the working FRA
examples that are part of the general LTspice XVII release typically
installed in directory
%HOMEPATH%\Documents\LTspiceXVII\examples\Educational\FRA\
Step 1: Identify a point in the SMPS feed back loop where a low impedance source is driving a high impedance input. Two places are useful for this, either in series with the feedback pin of the SMPS controller or between the output to the top of the resistor divider going to the feedback pin.
Step 2: Insert a voltage source here. This will be a time-domain sine wave that perturbs the feedback loop. Give it a value of "SINE(0 10m {Freq})" The choice of amplitude(here 10mV) will impact accuracy and the signal to noise of the method. The smaller the amplitude, the lower the signal to noise. But if the amplitude is too large, the system is not operating linearly and frequency response becomes less relevant since the frequencies are no longer independent.
Step 3: Label the nodes to either end of this voltage source "A" and "B" The direction of feedback should be from node A to node B. For example, if the voltage source is connected directly to the feedback pin, node B is the feedback pin and node A is the one on the other side of the voltage source.
Step 4: Paste the following .measure statements on the
schematic as a SPICE directive:
.meas Aavg avg V(a)
.meas Bavg avg V(b)
.meas Are avg (V(a)-Aavg)*cos(360*time*Freq)
.meas Aim avg -(V(a)-Aavg)*sin(360*time*Freq)
.meas Bre avg (V(b)-Bavg)*cos(360*time*Freq)
.meas Bim avg -(V(b)-Bavg)*sin(360*time*Freq)
.meas GainMag param 20*log10(hypot(Are,Aim)/hypot(Bre,Bim))
.meas GainPhi param mod(atan2(Aim,Are)-atan2(Bim,Bre)+180,360)-180
These .measure statements perform the Fourier transform of
nodes A and B and then compute the ratio of the resultant
complex voltages. The result is the complex open loop gain
of the system. The magnitude is given by GainMag in dB and
phase as GainPhi in degrees.
Step 5: Paste the following on the simulation command on the
schematic as a SPICE directive:
.param t0=.2m
.tran 0 {t0+10/freq} {t0}
Parameter t0 is the length of time required for the system
to come to steady state. You will probably have to run a
few simulations to determine an appropriate value for t0.
It occurs as the third parameter on the .tran command,
meaning is it the time the simulator should start saving
data. This prevents the .meas statements of Step 4 from
using this data in the analysis. This is done because
initial transient conditions might not be operating within
the small perturbations from regulation that could be
considered small signal response.
Step 6: Choose which frequency or frequencies at which to perform
the analysis. To do a single frequency, simply add this
SPICE directive:
.param Freq=15K
and run the simulation. The output of the .meas statements
are in the error log which you can view after running the
simulation with menu command View=>SPICE Error Log. You can
run the simulation at multiple frequencies by placing the
following SPICE directive on the schematic:
.step oct param freq 50K 100K 5
This directive tells LTspice to run the simulation at
frequencies from 50kHz to 100kHz using 5 points per octave.
To plot this as a Bode plot, after the simulations complete,
execute menu command View=>SPICE Error Log and then right
click menu "Plot .step'ed .meas data" At this point, the
Bode plot will not have any data ploted. so right click
again and execute menu command "Visible Traces" and then
select gain.
Armed with the above technique, one might feel ready to go and conquer SMPS design with Bode analysis of the feedback loop. I understand the temptation. It'd be rewarding if one could traverse the feedback loop identifying the components that gave rise to the poles and zeros, strategize which zeros to move to cancel which poles, and synthesize component values for the compensation network components to achieve a stable feedback loop. But that's pretty much exactly what you can't do with this technique or any other frequency domain technique. Let me explain why.
Let's consider a typical fixed-frequency, peak-current mode switcher
such as that in
%HOMEPATH%\Documents\LTspiceXVII\examples\Educational\FRA\Eg3.asc
The controller uses a flip-flop which is set by a clock pulse and
turns on the switch which ramps the inductor current up. Once the
peak switch current is proportional to the voltage on the output of
the error amplifier, the flip-flop is reset, the switch turns off and
the controller sits idle while until the next clock pulse sets the
flip-flop again. Since average current is proportional to peak
current up to a geometrical factor, if we average over one clock
cycle this flip-flop controlled-switch behaves like a
transconductance. That is the current through the switch is
proportional to the voltage on the output of the error amplifier.
Now if continue on along the feedback path, we have the inductor
in series with the switch current. Since the switch is a current
source, the series impedance of the inductor, even though it is
reactive, causes no phase shift. This is actually the point to
current-mode control and why you buy that controller. Continuing on
the feedback path, we are now at the output of the SMPS. The output
filter capacitor(C4) gives rise to one pole. The output is then
divided by the feedback resistive divider and compared to a reference
voltage at the feedback pin. The difference between the divided
output and the reference voltage is the error voltage. This error
voltage is amplified the the error amplifier to be a current which
flows out of the error amplifier. But it is the voltage on the
output of the error amplier and not the current flowing out of it
that determines switch current so to complete traversing the feedback
loop, we need to convert that current to a voltage. We could do that
with a resistor and that would work, but a much better idea is to use
a capacitor(C1) because that will maximize the open loop DC gain to
keep the output regulated to a stiff voltage. That capacitor makes
a second pole.
Now, since each pole can cause a phase shift infinitesimally close to 90° and the controller must cause some additional delay, one might think that some circuit design is necessary to ensure a stable feedback loop. But that's not really the case particularly if one is using an aluminum electrolytic cap output filter capacitor because it has ESR and that will put a zero in the response. Also, since we buy compensation cap C1 a series resistor, R1, that also puts another zero in the response. Further, the delay from the controller is a very small fraction of the switching frequency. At the loop crossover frequency and below, that delay is negligible. This all means that the loop is stable and it isn't possible to synthesize component values since the loop is stable for all component values. This argument basically is pointing out that as soon as the signal regulated by the feedback loop of a current mode SMPS is well- described by the current averaged over one switching cycle, that loop is stable.
If the output filter cap isn't an aluminum electrolytic but a ceramic capacitor, the ESR of a ceramic capacitor isn't high enough to substantially impact the stability of the SMPS. So the loop response, per the previous discussion, would now be two poles and one zero so it should still be stable independent of the specific component values of the output filter cap or RC circuit attached to the error amplifier output. But it would be appropriate to discuss the limits of applicability of the above analysis. There is an effect that degrades from the accuracy of the above description of current mode SMPS stability. The average current isn't proportional to the peak current over variation of output voltage because the duty cycle, and hence ripple current, changes with output voltage so the same peak current that trips the controller flip-flop does not give the same average current over changes in output voltage. This means that the transfer function from the voltage on the output of the error amplifier to the current flowing into the inductor isn't perfectly described as a transconductance, but a transconductance shunted with some real impedance. This impedance is typically several Ohms, which while very large compared to the on resistance of a MOSFET, it is less than infinite. This is not desirable from a stability point of view since the inductor is no longer fed from a current source and its reactance can cause some phase shift. This situation is further degraded by slope compensation. Slope compensation is the fix for a subharmonic oscillation that occurs in fixed frequency current mode controllers operating at high duty cycle. The technique entails adding a spoofed current to the measured switch current and using that quantity to reset the controller's flip-flop. The impact of using a quantity other than current to reset the flip-flop reduces the impedance of the current source feeding the inductor so the inductor's reactance causes yet more phase shift.
By and large, I find it pretty hard to make a current-mode SMPS unstable. For example, if you use an inductance value that is too high by an order of magnitude or two, then inductor ripple curent becomes very small and the spoofed current of the slope compenstation controls the flip-flop reset. That will reduce the impedance of the switched source driving this inductance to the impedance of the MOSFET Rds(on) so the inductor creates another pole in the loop and that causes instablity. But in that situation, even though you're using a current mode controller, the power supply is actually running in voltage mode. Small signal linear analysis of voltage mode power supplies is quite useful because unless the feedback loop has been contrived to cancel one of the poles, the power supply will oscilate and may blow itself up the first time it is turned on. Current-mode supplies are quite different. While it is possible to do small-signal linear analsys of a current-mode switcher, there just isn't much engineering to be accomplished with the method since the feedback loop is stable as long as the power supply really is operating in current mode.
The last advise I can offer answers how one can be sure that a SMPS is stable and operating in current mode. The answer is to start with the schematic on the front page of the datasheet. The critical information there are the inductance value, output filter capacitance, and external compensation component values. Some datasheets give equations for computing these values, but I just start with those values and adjust using time domain simulation to evaluate the response. After all, the whole point of frequency domain analysis is to improve the time domain response. With current-mode switchers, it usually more direct to jump right to time-domain simulation to check overshoot since stablity has already been achived.
1] The discussion is restricted to minimum-phase systems.
2] R. David Middlebrook, "Measurement of Loop Gain in Feedback Systems", International Journal of Electronics (vol 38, no. 4, pages 485-512, April 1975).